Race for faster chips..

The Race for faster chips is on...
As the Moore's Law goes - "The number of transistors on integrated circuits would double every 18 months or so " - this remarkable rate of advancement has resulted in smaller feature sizes, improved manufacturing techniques, which allow making larger chips and wafers and more efficient circuit designs and materials, which allow better circuit performance.



But as the size of transistors shrank and chips became more & more crammed - the fundamental physical constraints came into play. In fact, the consequences of miniaturization were predicted to be opposite to their original purpose, with smaller transistors performing even worse.

A different approach is to work with multiple processor chips working in parallel. But all such approaches will plateau some 10 or 15 years later, paving the way for research in nanoelectronics. As the components involved achieve smaller dimensions, their quantum effects cannot be ignored.

IBM, on Wednesday announced that it has devised a way to triple the amount of memory stored on microchips and double the performance of processors. This development is expected to speed the movement of graphics in gaming, networking, and other image intensive, multi-media applications.



In a statement, Subramanian Iyer, Development Director, IBM, said, "IBM is effectively doubling microprocessor performance beyond what classical scaling alone can achieve. As semiconductor components have reached the atomic scale, design innovation at the chip-level has replaced materials science as a key factor in continuing Moore's Law. Today's announcement further demonstrates IBM's leadership in this critical area of microprocessor design innovation."

IBM plans to use dynamic RAM (DRAM) instead of static RAM (SRAM) as the embedded memory cache built onto each chip. The change will allow each chip to store its data in one-third the area and use one-fifth the electricity for standby power. IBM is already using the new embedded DRAM (eDRAM) in 65nm prototype chips, and plans to roll it out commercially by 2008 for its entire range of 45nm chips, including its Power line.